Nanotubes (NTs), generally, and Carbon Nanotubes (CNTs), specifically, are viewed to be a new key element for future electronics. In the CNT, especially single walled carbon nanotubes (SWCNTs), such unique properties as quantization of the electron spectrum, ballistic electron propagation along the tube, current densities as high as 109 A/cm2, existence of the semiconductor phase, possibilities for n- and p-doping with a high carrier mobilities, as well as excellent thermal conductance, make nanotubes a great candidate for future novel high-speed, high efficiency electronic and photonic devices.
A key element widely used in the electronic logic circuits is CMOS, wherein both switching states consume minimum energy, see. e.g. J. R. Brews in High-speed Semiconductor Devices, J. Wiley & Sons, New York, p. 139, 1990. It is therefore important for future nanotube applications to reproduce such an element using CNT technology. Such attempts have been carried out in many research places worldwide.
FIG. 1a shows as a Prior Art two CNT FETs in series, with n-type and p-type channel field-effect transistors (FET) forming the CMOS circuit, see V. Derycke et al, Nano Letters 1, p. 453, 2001. The CNT CMOS is made from a single nanotube extended between source and drain metal contacts deposited on the Si substrate, while the controlling gate electrodes are made simply by placing the nanotube on top of the SiO2 insulating layer on the n+Si substrate. To convert originally p-type CNT into n-type, one of the transistors has been subjected to annealing in vacuum. The resultant effect of voltage switch is shown in FIG. 1b. 
The proof-of-concept design, used in V. Derycke's work, where a single nanotube is placed on the substrate between the contacts, is utilized in essentially all publication on this topic, for both CMOS circuit and individual transistors (see also E. Ungersboeck, et al, IEEE Transactions on nanotechnology, V 4, p. 533, 2005). The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing.
The patent application Ser. No. 11/705,577 filed by A. Kastalsky on February 2007, which issued as U.S. Pat. No. 7,851,784 describes several nanotube array devices and method for their fabrication. Shown in FIG. 2 is the nanotube array FET (the direction of the nanotube array is normal to the drawing plane) in which the nanotubes are grown normal to the substrate and the gate electrode 21 is attached to the sidewall of every nanotube 27 in the array through a layer of insulator 24. The key element is the metal layer 21 in the middle of the nanotube length, sandwiched between two insulator layers 22 and 23. During deposition of the first insulator layer 22, a thin layer of insulation material will also be deposited on the nanotube walls, thereby forming a gate insulator layer 24 around each nanotube. It is then followed by deposition of the gate metal layer 21 and the insulator layer 23. After polishing of the insulator layer 23 and exposure of the nanotube tips, the top metal layer 25 (the drain electrode) is deposited to complete the structure.